1. Field of the Invention
The invention relates to the field of memories such as random access memories (RAMs) having memory cells coupled to bitlines.
2. Prior Art
Integrated circuits frequently include RAMs embedded within a larger circuit. For instance, microprocessors sometimes include on-board cache memories and similarly, integrated circuits designed for communications sometimes include RAM for buffering data between networks or a network and a computer. In these instances, the memory is frequency not directly accessible from external terminals. That is, all the address lines and input/output lines of the memory may not be directly coupled to terminals or pads which are externally accessible. For this reason, the testing of these memories becomes more difficult and often requires that the integrated circuit include circuitry for testing the memory. This is in contrast to a memory "chip" such as commercially available DRAM or SRAM chips where all the address lines and data lines are coupled to terminals of the chip allowing the memory array to be fully accessed for testing without special circuitry.
FIG. 1 illustrates a prior art memory embedded in an integrated circuit. The memory includes an array 10 of memory cells having a plurality of bitline pairs which extend from write drivers 11 to the sense amplifiers 12. A single bitline pair and a single memory cell 18 connected to the bitline pair are shown in FIG. 1. The cells which are often bistable (static) memory cells are selected by word lines such as word line 19. A row of cells is selected by an active word line either for writing data by write drivers 11 or for sensing data from the selected cells by the sense amplifiers 12. Both the writing and reading of data occurs over the bitlines. The write drivers 11, memory array 10 and sense amplifiers 12 are well-known in the prior art and are used in numerous integrated circuits.
For the illustrated prior art of FIG. 1, data is written into the memory from a register 13. The register 13 is a parallel/serial, shift/load register which receives data (in parallel) over lines 15. For the illustrated memory the register 13 has 70 stages to accommodate the memory array 10 which is 70 cells wide. That is, there are 70 pairs of bitlines, 70 write drivers 11 and 70 sense amplifiers 12. Data read from the memory through the sense amplifiers 12 is coupled to a register 14. The register 14 is a parallel/serial, shift/load register.
For purposes of testing the memory array 10 a bit pattern representing data is typically written into the memory and then read from the memory. The data read from the memory is then compared with the data written into the memory to determine if the data read from the memory is the same as the data written into the memory. This testing verifies that the array and the drivers and sense amplifiers are functioning properly. Test patterns of ones and zeros are used for each of the rows of memory cells to fully exercise the memory as is well-known in the art.
For the memory illustrated in FIG. 1, the output of the register 14 is compared in the compare circuit 17 with a bit pattern stored in the register 13. The pattern stored in the register 13 is coupled to the compare circuit 17 through the lines 16. For purposes of testing the memory a bit pattern is transferred into the register 13 either serially or in parallel and then written into a selected row of cells in the memory over the bitlines. Then a read cycle is used to access the cells and read the data over the bitlines using the sense amplifiers 12. The data defining the bit pattern is placed into the register 14. This bit pattern is then coupled from the register 14 to the compare circuit 17 and compared with the contents of the register 13. If the contents are equal, the data was faithfully written into and read from the memory cells. In this manner each row of cells in the array 10 is tested.
A problem with the circuit of FIG. 1 is that the bit pattern from the register 13 must be coupled to the compare circuit 17 as shown by the lines 16. For the illustrated embodiment, at least 70 lines are needed, one for each bit, if the testing is to be accomplished quickly. The 70 lines 16 are routed on the substrate spaced apart from the array 10 and as such, require substrate area. The substrate area for these 70 lines, as can be appreciated, is a relatively significant amount of area when compared to the RAM itself. (In some cases more than one RAM is used in an integrated circuit.)
It should be noted that the lines 16 cannot easily be routed over the top of the array 10. Generally, the array 10 requires use of all of the available metal layers of a process, and moreover, because of the sensitivity associated with the bitlines in the array, the coupling caused by additional lines over the array may affect the performance of the array.
As will be seen with present invention, the array 10 of FIG. 1 is tested without the use of the lines 16 and consequently, substrate area is saved as will be discussed.